74vhc86 ?quad 2-input exclusive-or gate ?992 fairchild semiconductor corporation www.fairchildsemi.com 74vhc86 rev. 1.4.0 f ebruary 2008 74vhc86 quad 2-input exclusive-or gate features high speed: t pd = 4.8ns (typ.) at v cc = 5v low power dissipation: i cc = 2? (max.) @ t a = 25? high noise immunity: v nih = v nil = 28% v cc (min.) power down protection is provided on all inputs low noise: v olp = 0.8v (max.) pin and function compatible with 74hc86 general description the vhc86 is an advanced high speed cmos quad exclusive or gate fabricated with silicon gate cmos technology. it achieves the high speed operation similar to equivalent bipolar schottky ttl while maintaining the cmos low power dissipation. an input protection circuit ensures that 0v to 7v can be applied to the input pins without regard to the supply voltage. this device can be used to interface 5v to 3v systems and on two supply systems such as battery back up. this circuit prevents device destruction due to mismatched supply and input voltages. ordering information device also available in tape and reel. specify by appending suffix letter ??to the ordering number. all packages are lead free per jedec: j-std-020b standard. order number package number package description 74vhc86m m14a 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow 74vhc86sj m14d 14-lead small outline package (sop), eiaj type ii, 5.3mm wide 74vhc86mtc mtc14 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74vhc86n n14a 14-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide
?992 fairchild semiconductor corporation www.fairchildsemi.com 74vhc86 rev. 1.4.0 2 74vhc86 ?quad 2-input exclusive-or gate connection diagram pin description logic symbol ieee/iec truth table pin names description a 0 ? 3 inputs b 0 ? 3 inputs o 0 ? 3 outputs abo lll lhh hlh hhl
?992 fairchild semiconductor corporation www.fairchildsemi.com 74vhc86 rev. 1.4.0 3 74vhc86 ?quad 2-input exclusive-or gate absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. recommended operating conditions (1) the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. note: 1. unused inputs must be held high or low. they may not float. symbol parameter rating v cc supply voltage ?.5v to +7.0v v in dc input voltage ?.5v to +7.0v v out dc output voltage ?.5v to v cc + 0.5v i ik input diode current ?0ma i ok output diode current ?0ma i out dc output current ?5ma i cc dc v cc / gnd current ?0ma t stg storage temperature ?5? to +150? t l lead temperature (soldering, 10 seconds) 260? symbol parameter rating v cc supply voltage 2.0v to +5.5v v in input voltage 0v to +5.5v v out output voltage 0v to v cc t opr operating temperature ?0? to +85? t r , t f input rise and fall time, v cc = 3.3v ?0.3v v cc = 5.0v ?0.5v 0ns/v 100ns/v 0ns/v 20ns/v
?992 fairchild semiconductor corporation www.fairchildsemi.com 74vhc86 rev. 1.4.0 4 74vhc86 ?quad 2-input exclusive-or gate dc electrical characteristics noise characteristics note: 2. parameter guaranteed by design. symbol parameter v cc (v) conditions t a = 25? t a = ?0? to +85? units min. typ. max. min. max. v ih high level input v oltage 2.0 1.50 1.50 v 3.0?.5 0.7 x v cc 0.7 x v cc v il low level input v oltage 2.0 0.50 0.50 v 3.0?.5 0.3 x v cc 0.3 x v cc v oh high level output voltage 2.0 v in = v ih or v il i oh = ?0? 1.9 2.0 1.9 v 3.0 2.9 3.0 2.9 4.5 4.4 4.5 4.4 3.0 i oh = ?ma 2.58 2.48 4.5 i oh = ?ma 3.94 3.80 v ol low level output voltage 2.0 v in = v ih or v il i ol = 50? 0.0 0.1 0.1 v 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 3.0 i ol = 4ma 0.36 0.44 4.5 i ol = 8ma 0.36 0.44 i in input leakage current 0?.5 v in = 5.5v or gnd ?.1 ?.0 ? i cc quiescent supply current 5.5 v in = v cc or gnd 2.0 20.0 ? symbol parameter v cc (v) conditions t a = 25? units t yp. limits v olp (2) quiet output maximum dynamic v ol 5.0 c l = 50pf 0.3 0.8 v v olv (2) quiet output minimum dynamic v ol 5.0 c l = 50pf ?.3 ?.8 v v ihd (2) minimum high level dynamic input voltage 5.0 c l = 50pf 3.5 v v ild (2) maximum low level dynamic input voltage 5.0 c l = 50pf 1.5 v
?992 fairchild semiconductor corporation www.fairchildsemi.com 74vhc86 rev. 1.4.0 5 74vhc86 ?quad 2-input exclusive-or gate ac electrical characteristics note: 3. c pd is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. average operating current can be obtained by the equation: i cc (opr.) = c pd ?v cc ?f in + i cc / 4 (per gate). symbol parameter v cc (v) conditions t a = 25? t a = ?0? to +85? units min. typ. max. min. max. t phl , t plh propagation delay 3.3 ?0.3 c l = 15pf 7.0 11.0 1.0 13.0 ns c l = 50pf 9.5 14.5 1.0 16.5 5.0 ?0.5 c l = 15pf 4.8 6.8 1.0 8.0 ns c l = 50pf 6.3 8.8 1.0 10.0 c in input capacitance v cc = open 4 10 10 pf c pd po w er dissipation capacitance (3) 18 pf
?992 fairchild semiconductor corporation www.fairchildsemi.com 74vhc86 rev. 1.4.0 6 74vhc86 ?quad 2-input exclusive-or gate physical dimensions figure 1. 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchild s worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductor s online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/ land pattern recommendation notes: unless otherwise specified a) this package conforms to jedec ms-012, variation ab, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x145-14m e) drawing conforms to asme y14.5m-1994 f) drawing file name: m14arev13 pin one indicator 8 0 seating plane detail a scale: 20:1 gage plane 0.25 x45 1 0.10 c c b c a 7 m 14 b a 8 see detail a 5.60 0.65 1.70 1.27 8.75 8.50 7.62 6.00 4.00 3.80 (0.33) 1.27 0.51 0.35 1.75 max 1.50 1.25 0.25 0.10 0.25 0.19 (1.04) 0.90 0.50 0.36 r0.10 r0.10 0.50 0.25
?992 fairchild semiconductor corporation www.fairchildsemi.com 74vhc86 rev. 1.4.0 7 74vhc86 ?quad 2-input exclusive-or gate physical dimensions (continued) figure 2. 14-lead small outline package (sop), eiaj type ii, 5.3mm wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchild s worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductor s online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/
?992 fairchild semiconductor corporation www.fairchildsemi.com 74vhc86 rev. 1.4.0 8 74vhc86 ?quad 2-input exclusive-or gate physical dimensions (continued) figure 3. 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchild s worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductor s online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/ c. dimensions are exclusive of burrs, mold flash, and tie bar extrusions f. drawing file name: mtc14rev6 r0.09 min 12.00 top & botto m 0.43 typ 1.00 d. dimensioning and tolerances per ansi y14.5m, 1982 r0.09min e. landpattern standard: sop65p640x110-14m 0.65 6.10 1.65 0.45 a. conforms to jedec registration mo-153, variation ab, ref note 6 b. dimensions are in millimeters
?992 fairchild semiconductor corporation www.fairchildsemi.com 74vhc86 rev. 1.4.0 9 74vhc86 ?quad 2-input exclusive-or gate physical dimensions (continued) figure 4. 14-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchild s worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductor s online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/ 14 8 7 1 notes: unless otherwise specified a) this package conforms to jedec ms-001 variation ba b) all dimensions are in millimeters. c) dimensions are exclusive of burrs, mold flash, and tie bar extrusions. d) dimensions and tolerances per asme y14.5-1994 e) drawing file name: mkt-n14arev7 6.60 6.09 8.12 7.62 0.35 0.20 19.56 18.80 3.56 3.30 5.33 max 0.38 min 1.77 1.14 0.58 0.35 2.54 3.81 3.17 8.82 (1.74)
?992 fairchild semiconductor corporation www.fairchildsemi.com 74vhc86 rev. 1.4.0 10 trademarks th ef ollowing includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its global s ubsidiaries, and is not intended to be an exhaustive list of all such trademarks. acex build it now coreplus crossvolt ctl current transfer logic ecospark ezswit ch * fairchild fairchild semiconductor fact quiet series fact fast fastvcore flashwriter ? fps frfet global power resource sm green fps green fps e-series gto i-lo intellimax isoplanar m egabuck mi crocoupler microfet micropak mi llerdrive mo ti on-spm optologic optopl anar pdp-spm pow er220 pow er247 poweredge power-spm po we rtrench pr ogrammable active droop qfet qs qt optoelectronics quiet series rapidconfigure smart start spm stealth s uperfet su persot -3 s upersot -6 s upersot -8 syncfet the power franchise tinyboost tinybuck tinylogic tinyopto tinypower tinypwm tinywire serdes uhc ultra f rfet unifet vcx *ezswi tch and flashwriter are trademarks of system general corporation, used under license by fairchild semiconductor. disc laimer fa i rchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any pro duct or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these speci fications do not expand t he terms of fairchild? wo rl dw ide terms and conditions, specifically the warranty therein, which covers these products. life support policy fa i rchild s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems wh ic h, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform wh en properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. pr oduct status definitions defi nition of terms da tasheet identification product status definition ad vance information form first production ative or in design this datasheet contains the design specifications for product development. specifications may change in any manner without notice. pr eliminary this datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to ma ke c hanges at any time without notice to improve design. no identification needed full production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice to improve the des i gn. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. rev. i32 74vhc86 ?quad 2-input exclusive-or gate
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